1. Field of the Invention
The present invention relates to an active matrix liquid crystal display (AMLCD) including an active panel with thin film transistors (TFT) and pixel electrodes arranged in a matrix pattern, and more particularly, to a simplified method of manufacturing the active panel in the AMLCD.
2. Discussion of the Related Art
Among display devices for showing visual images on a screen, thin film type flat panel display devices are highly favored because of their light weight and easy adaptability. Especially, active research activities have focused on the development of liquid crystal display devices because of their high resolution and fast response time suitable for display of motion picture images.
A liquid crystal display device works by using polarization and optical anisotrophy of a liquid crystal. By controlling the orientation of liquid crystal molecules having rod shape through polarization technique, transmission and interception of a light through the liquid crystal are achieved due to the anisotrophy of the liquid crystal. This principle is applied to the liquid crystal display device. AMLCDs having TFTs arranged in a matrix pattern and pixel electrodes connected to the TFTs provide high quality images and are now widely used. The structure of a conventional AMLCD will now be described.
A color filter panel of an LCD includes a sequential arrangement of red, blue and green color filters on a transparent substrate at pixel positions designed in a matrix pattern. Among these color filters, black matrixes are formed in a lattice pattern. On the color filters, a common electrode is formed.
An active panel of an LCD includes pixel electrodes designed in a matrix pattern and formed on a transparent substrate. Along the column direction of the pixel electrodes, signal bus lines are formed, and along the row direction of the pixel electrodes, data bus lines are formed. At a corner of a pixel electrode, a TFT for driving the pixel electrode is formed. A gate electrode of the TFT is connected with a signal bus line (or a gate bus line). A source electrode of a TFT is connected with a data bus line (or a source bus line). Additionally, a storage capacitor electrode may be formed in parallel with the gate bus line and crossing the pixel electrode. A pad is formed at the end portion of each bus line.
The color filter panel and the active panel are bonded together with a certain distance therebetween (i.e., a cell gap) to face each other. Liquid crystal material fills the cell gap to complete a liquid crystal panel of an LCD.
The method of manufacturing a liquid crystal display device is very complicated including many processes combined together. The method of manufacturing an active panel having TFTs and pixel electrodes is even more complicated. Therefore, it is important to simplify the method for manufacturing an active panel to reduce the possibility of defects during the manufacture process.
A conventional method for manufacturing an active panel is described with reference to FIG. 1 showing a plan view of an active panel, and FIGS. 2A-2H showing cross-sectional views taken along line II--II of FIG. 1.
As shown in FIGS. 1 and 2A, aluminum or aluminum alloy is vacuum deposited on a transparent substrate 11 and patterned by using a first mask to form gate bus lines 13, gate pads 15, gate electrodes 17, source pads 25 and a shorting bar 21. The gate bus line 13 connects gate electrodes 17 disposed in a column direction. The gate pad 15 is disposed at the end of the gate bus line 13. The shorting bar 21 makes a connection between the gate pad 15 and the source pad 25 and surrounds the periphery of the substrate 11. The source pad 25 is formed at the end portion of source bus lines 23 which are to be formed later. Here, the gate bus line 13 may be used for forming a storage capacitor electrode.
As shown in FIG. 2B, using the shorting bar 21 as an anode for anodizing, the elements formed of metal as described above are anodized to form an anodic oxide film 13a on the surface. This is to prevent a hill-lock on the aluminum surface. Since the gate electrode 17, gate pad 15, gate bus line 13 and source pad 25 are connected with the shorting bar 21, connection of the shorting bar 21 with an anode facilitates the anodizing of the elements. Here, the gate pad 15 and the source pad 25 are covered by using a second mask in order not to form an anodic oxide film on their surfaces.
As shown in FIG. 2C, silicone oxide or silicone nitride is vacuum deposited on the substrate including the lines and pads to form a gate insulating layer 29. Then, an intrinsic semiconductor material and an impure semiconductor material are deposited sequentially and patterned by using a third mask to form a semiconductor layer 31 and an impure semiconductor layer 33.
As shown in FIG. 2D, a first gate contact hole 51 on the gate pad 15 and a first source contact hole 61 on the source pad 25 are formed by using a fourth mask. Here, the contact holes 51 and 61 expose a portion of the gate pad and a portion of the source pad, respectively, which are not anodized.
As shown in FIG. 2E, Chromium or chromium alloy is vacuum deposited and patterned by using a fifth mask to form a source electrode 27, a drain electrode 37 and source bus lines 23 on the impure semiconductor layer 33. In addition, chromium or chromium alloy is also deposited on the gate pad 15 and source pad 25. The first source contact hole 61 connects the source bus line 23 with the source pad 25. Here, the chromium layer on the source pad is to protect the aluminum layer underneath and is used as an source pad intermediate electrode 67 to connect with a source pad connection terminal 65 which is to be formed later. Similarly, the chromium layer on the gate pad 15 connects the aluminum layer and a gate pad connection terminal 55, which is to be formed later, through the first gate contact hole 51 forming a gate pad intermediate electrode 57. The exposed portion of the impure semiconductor 33 between the source electrode 27 and drain electrode 37 is removed by using the source electrode 27 and drain electrode 37 as masks.
When it is necessary to form a storage capacitor electrode 19 the storage capacitor electrode 19 in (n)th row is formed to overlap the gate line 13 in (n-1)th row.
Next, as shown in FIG. 2F, an insulating material, such as silicone oxide or silicone nitride, is vacuum deposited on the substrate including the source electrode 27 and drain electrode 37 to form a protection layer 35. The protection layer 35 is patterned by using a sixth mask to form a second gate contact hole 53 on the gate pad 15, a second source contact hole 63 on the source pad 25, and a drain contact hole 71 on the drain electrode 37. The gate pad 15 is connected with an external terminal through the second gate contact hole 53, the source pad 25 is connected with an external terminal through the second source contact hole 63, and the drain electrode 37 is connected with a pixel electrode 39 (to be formed later) through the drain hole 71.
In case of forming the storage capacitor electrode 19, the protection layer 35 over the storage capacitor electrode 19 is removed to form a storage capacitor contact hole 75, through which the storage capacitor electrode 19 is connected with the pixel electrode 39.
As shown in FIG. 2G, part of the shorting bar 21, which is made of aluminum and connected to the gate bus line 13, the gate electrode 17, the gate pad 15 and the source pad 25, is removed to complete the final structure of the active panel by using a seventh mask.
As shown in FIG. 2H, indium-tin oxide is vacuum deposited on the surface including the protection layer 35 and patterned by using an eighth mask to form pixel electrodes 39, gate pad connection terminals 55 and source pad connection terminals 65.
As described above, eight masks are used during the formation of the active panel. The more mask steps are used, the worse the quality of the LCD is likely to be. Moreover, the patterning process including the masking steps generally takes a relatively long time. Therefore, elimination of even one mask step can reduce the cost and increase the production yield.